CAUTION:
Before servicing this chassis, it is important that the service technician read the "Safety
Precautions" and "Product Safety Notices" in this service manual.
ATTENTION:
Avant d'effectuer l'entretien du châassis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die ,,Sicherheitshinweise" und ,,Hinweise
zur Produktsicherheit" in diesem Wartungshandbuch zu lesen.
SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH
Data
contained
within
this
Service
manual is subject to alteration for
improvement.
Les données fournies dans le présent
manuel d'entretien peuvent faire l'objet
de modifications en vue de perfectionner
le produit.
Die
in
diesem
Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
Digital Versatile Disk
August 2004
No. 9403
DV-P345UK
DV-P345E
2
1. GENERAL DESCRIPTION
1.1 ZR36768
The ZR36768 Disc Loader Controller and Decoder Device can control disc loaders and read
bitstreams using the following media: DVD-ROM, DVDRW, CD-DA, CD-ROM, CD-R and CD-R/W
discs. The device can decode bitstreams and process navigation data of the following formats:
DVD-Video, DVD-Audio, CD-DA, VCD (Video-CD), SVCD (Super Video-CD) and MP3.
The features of this chip can be listed as follows:
Disc loader control and bitstream processing
·
8 analog inputs (low frequency) for servo errors and RF signals envelope monitoring
·
11 actuators drive or control outputs. Two analog outputs through 11 bits DACs (e.g. for the
tracking and focus coils), and 9 PWM outputs divided into two type groups: High frequency,
"uniform" type PWMs (e.g. for the spindle and sled motor drives), and lower frequency
"regular" type PWMs, which can be used e.g. for programmed tray motion or RF amplifier
parameter setting.
·
Processing of spindle and sled position read-back devices
·
All servo loop closure, closed loop control and error handling.
·
Bitstream extraction using AGC, bit clock frequency detection and phase lock loop, adaptive
threshold calculations, Viterbi bit decision, defect detection, frame sync detection and EFM/P
conversion.
·
CD sub-code extraction and processing.
·
CD ECC for all CD types. CD EDC for Mode 1 discs
·
DVD ECC and EDC.
·
Track buffer and re-try management
Decoding
·
Single chip solution for playback of DVD-Video, DVD-Audio Video-CD, Super Video-CD, CD-
DA, and MP3 from CD-ROM, CD-R or CD-R/W.
·
Decoding and display of high resolution MPEG 1 and MPEG 2 still image sequences
(including ASVs from DVD-Audio but without the transition effects).
·
Decoding of Dolby AC-3, DTS or MLP multi-channel audio.
·
Decoding of MPEG 1 or MPEG 2 layer II mono, stereo, or multi-channel audio. Decoding of
MPEG 1 or MPEG 2 Layer 3 (MP3) mono and stereo audio.
·
PCM and LPCM audio playback from DVD-Video, DVD-Audio, Video-CD and CD-DA.
·
Decoding and playback of sub-picture (including Highlight), and closed captions ("line 21")
data from DVD-Video discs.
·
Interlaced digital and analog video output or progressive analog video output.
·
NTSC and PAL standards. PAL playback of NTSC discs and NTSC playback of PAL discs.
·
Special modes support like pause, slow motion, fast forward and reverse.
Post Processing
·
Audio down mixing, sample rate conversion, Dolby's pro-logic and 3D enhancement.
·
Karaoke mixing of decoded audio and two channels of input audio.
·
On-chip OSD engine with 32 color (24-bit YUV) palette, up to 8 levels of transparency; and
capability of blinking regions and vertical scrolling.
·
On-screen and off-screen OSD memory regions for animation support.
·
1/4 pixel and 1/4 line pan&scan
·
Horizontal and vertical up- and down-scaling with polyphase two-tap vertical and horizontal
interpolation.
3
·
Letterbox and Pan-scan display aspect ratio conversion (16:9 to 4:3)
·
Automatic frame rate conversion (e.g., 3/2 pull down) and format conversion (16:9, 4:3, 1:1).
·
EIA-608 compatible modulation of line 21 (NTSC) or line 22 (PAL) closed captions data over
the video output.
·
Edge adaptive, two fields, de-interlacing generating a progressive analog video output.
Interfaces
·
8-bit YUV 4:2:2 digital interlaced video output.
·
Composite, Y/C, YUV or RGB interlaced analog video output or component progressive
analog video output (using 10 bits on-chip DACs)
·
Internally generated video sync signals and internally generated audio port clock signals.
·
6/18/20/24-bit I2S or EIAJ serial audio outputs. 16 bit I2S EIAJ serial audio input
·
2 to 8 channels audio output. 2 channels audio input
·
S/PDIF output for compressed audio (including DTS) or reconstructed audio (according to
IEC 958 and its extensions).
·
Single 64-Mbit, single 16-Mbits and dual 16 Mbits SDRAMs (16 bits data)
·
Direct interface (through RF and servo amplifiers) to several types of disc loaders.
·
SW controlled GPIO to interface to IR remote control receiver, front panel concentrator, audio
DACs and ADC, etc.', e.g. using I2C, SPI and other protocols.
·
3 line serial general purpose slave interface (SSC)
·
2 UART interfaces for CPU SW debug
·
JTAG interfaces for CPU, ADP and DSP SW debug
Physical Features
·
Dual supply: 1.8V for the core and PLL, and 3.3V for the I/O and DACs.
·
208 pin, PQFP package.
·
TTL I/O levels. 5V tolerance on many inputs.
·
Single 27MHz crystal/clock input.
·
5 layer metal, 0.18 micron technology.
·
Less than 1.6 W power consumption during operation.
·
Several power-down modes
1.2 MEMORY
1.2.1
SDRAM Memory Interface
The ZR36768 provides 16-bit interface to DRAM memory devices used as OSD, MPEG
stream and video buffer memory for a DVD player. The maximum amount of memory supported
is 8 MB of Synchronous DRAM (SDRAM). The memory interface is configurable in depth to
support 64-Mb addressing.
1.3 DRIVE INTERFACES
The ZR36768 supports d
irect interface (through RF and servo amplifiers) to several types
of disc loaders.
1.4 FRONT PANEL
The front panel is based around a Futaba VFD and a Princeton front panel controller
chip, (PT6311). The ZR36768 controls the PT16311 using several control signals, (clock, data,
chip select). The infrared remote control signal is passed directly to the ZR36768 for decoding.
4
1.5 REAR PANEL
A typical rear panel supports:
- Six channel or two channel audio outputs
- Optical and coax S/PDIF outputs.
- Composite, S-Video, and SCART outputs
Outputs provided by ZR36768 are Composite, Y/C, YUV or RGB interlaced analog video output
or component progressive analog video output (using 10 bits on-chip DACs). DVD6110 rear
panel has Composite and S-video otputs on it.
ZR36768 provides 2 to 8 channels audio output. DVD6110 has 2 channels audio output on its
rear panel. The rear panel has S/PDIF serial stream and optical output generated by the
ZR36768. CS4392 Audio DACs are used for two channel audio output with ZR36768.
2. SYSTEM BLOCK DIAGRAM and ZR36768 PIN DESCRIPTION
2.1 ZR36768 PIN DESCRIPTION
Pin No
Pin Functions Direction
Description
CPU Interface (15 pins)
DUPTD0 //
O //
First debug UART data output //
153
GPCI/O[36]
I/O
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW
DUPRD0 //
I //
First debug UART data input //
152
GPCI/O[35]
I/O
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW
DUPTD1 //
O //
Second debug UART data output //
156
GPCI/O[38]
I/O
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW
DUPRD1 //
I //
Second debug UART data input //
155
GPCI/O[37]
I/O
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW
GPCI/O[20]
I/O //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
106
CPUNMI //
I //
CPU non-maskable interrupt input //
SDATA[0] //
I //
SERVO channel sample data input for AFE by-pass //
PM[0]
O
Probe mux data output
ICGPCI/O[0]
I/O //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
108
to the CPU //
AOUT[3] //
O //
Serial output of digital stereo audio //
SDATA[1] //
//
SERVO channel sample data input for AFE by-pass //
PM[1]
O
Probe mux data output
IDGPCI/O[0] //
I/O //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
109
to the DSP //
5
SDATA[2] //
I //
SERVO channel sample data input for AFE by-pass //
PM[2]
O
Probe mux data output
149,147 GPCI/O[34-31] I/O
General purpose input/output pins, monitored/controlled by the CPU or DSP
145,136
SW.
ICGPCI/O[5,4]
I/O
General purpose input/output pins monitored/controlled by the CPU or DSP
148,146
SW. When input, the pins can be used as general purpose external interrupts
to the CPU
IDGPCI/O[3]
I/O
General purpose input/output pins, monitored/controlled by the CPU or DSP
150
SW. When input, the pins can be used as general purpose external interrupts
to the DSP
PLL Signals (4 pins)
139
RESET#
ID
Reset input (active low)
142
GCLKP
ID
27.000MHz clock or crystal input for main processing clock generation.
141
XO
AO
Output to a crystal that is connected to GCLK. If a crystal is not used at
GCLK, XO must be left not connected.
143
GCLKA
ID
27.000MHz clock input for audio master clock generation. In normal operation
must be connected to GCLKP
Analog Video Port, (5 pins)
CVBS/G/Y
AO
When the I64 outputs composite video, this line is CVBS
158
(DAC A)
When the I64 outputs RGB, this line is the Green output
When the I64 outputs YUV, this line is the Y output
Y/R/V/C
AO
When the I64 outputs the composite video, this line is Y
161
(DAC B)
When the I64 outputs RGB, this line is the Red output
When the I64 outputs YUV, this line is the V output
When the I64 outputs SCART, this line is the C output
C/B/U
AO
When the I64 outputs the composite video, this line is C
162
(DAC C)
When the I64 outputs RGB, this line is the Blue output
When the I64 outputs YUV, this line is the U output
159
CVBS/C/Y
AO
The output on this line can be either CVBS or C or Y
(DAC D)
The selection is independent of the selection of the other three DACs.
163
RSET
AI
Resistive load for gain adjustment of the DACs
Digital Video Port, CPU, DSP and ADP de-bug (11 pins)
VID[7] //
O //
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
ICETMS //
I //
ADP debug interface //
128
DJTMS //
I //
DSP debug interface //
GPCI/O[26] //
I/O //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
DACTEST[7]
I
DACs test input
VID[6] //
O //
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
ICETDI //
I //
ADP debug interface //
129
DJTDI //
I //
DSP debug interface //
ICGPCI/O[2]//
I/O //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
to the CPU//