© 2003-10 PRINTED IN JAPAN
B51-8664-00 (N) 179
UHF FM TRANSCEIVER
CIRCUIT DESCRIPTION ............................ 2
SEMICONDUCTOR DATA ........................ 8
COMPONENTS DESCRIPTION ................ 9
PARTS LIST ............................................. 10
EXPLODED VIEW .................................... 17
PACKING ................................................. 18
RESETTING THE TRANSCEIVER ........... 19
ADJUSTMENT ........................................ 20
TERMINAL FUNCTION ........................... 27
DISPLAY UNIT (X54-3450-10) ............ 28
TX-RX UNIT (X57-686X-XX) ............... 30
SCHEMATIC DIAGRAM .......................... 34
BLOCK DIAGRAM ................................... 38
LEVEL DIAGRAM .................................... 40
SPECIFICATION ................... BACK COVER
The receiver utilizes double conversion. The first IF is
49.95MHz and the second IF is 450kHz. The first local oscil-
lator signal is supplied from the PLL circuit.
The PLL circuit in the transmitter generates the necessary
frequencies. Figure 1 shows the frequencies.
The receiver is double conversion superheterodyne. The
frequency configuration is shown in Figure 1.
Front-end RF Amplifier
An incoming signal from the antenna is applied to an RF
amplifier (Q353) after passing through a transmit/receive
switch circuit (D603, D604 and D605 are off) and a BPF
(L359, L358 L360, L361 and varactor diodes : D353, D354,
D355). After the signal is amplified (Q353), the signal is fil-
tered by a BPF (L354, L355 and varactor diodes: D351, D352)
to eliminate unwanted signals before it is passed to the first
The voltage of these diodes are controlled by tracking the
CPU (IC101) center frequency of the band pass filter. (See
The signal from the RF amplifier is heterodyned with the
first local oscillator signal from the PLL frequency synthesizer
circuit at the first mixer (Q352) to create a 49.95MHz first
intermediate frequency (1st IF) signal. The first IF signal is
then fed through one pair of monolithic crystal filter (MCF :
XF351) to further remove spurious signals.
The first IF signal is amplified by Q351, and then goes to
IC301 (FM processing IC). The signal is heterodyned again
with a second local oscillator signal within IC301 to create a
450kHz second IF signal. The second IF signal is then fed
through a 450kHz ceramic filter (Wide : CF301, Narrow :
CF302) to further eliminate unwanted signals before it is am-
plified and FM detected in IC301.
Nominal center frequency
±5.0kHz or more at 3dB
35dB stop bandwidth
±20.0kHz or less
1.0dB or less
5.0dB or less
80dB or more at fo
40dB or more
Crystal filter (L71-0620-05) : XF351
Nominal center frequency
±6.0kHz or more
±12.5kHz or less
2.0dB or less
6.0dB or less
35.0dB or more within fo
Ceramic filter (L72-0993-05) : CF301
Nominal center frequency
±4.5kHz or more
±10.0kHz or less
2.0dB or less
6.0dB or less
60.0dB or more within fo
Ceramic filter (L72-0999-05) : CF302
Wide/Narrow Switching Circuit
The Wide port (pin 65) and Narrow port (pin 64) of the CPU
is used to switch between ceramic filters. When the Wide
port is high, the ceramic filter SW diodes (D303, D302) cause
CF301 to turn on to receive a Wide signal.
When the Narrow port is high, the ceramic filter SW diodes
(D303, D302) cause CF302 to turn on to receive a Narrow sig-
nal. (See Fig. 3.)
AF Signal System
The detection signal from IF IC (IC301) goes to D/A con-
verter (IC161) to adjust the gain and is output to AF filter
(IC251) for characterizing the signal. The AF signal output
from IC251 and the DTMF signal, BEEP signal are summed
and the resulting signal goes to the D/A converter (IC161).
The AFO output level is adjusted by the D/A converter. The
signal output from the D/A converter is input to the audio
power amplifier (IC252). The AF signal from IC252 switches
between the internal speaker and speaker jack (J1) output.
(See Fig. 4.)
The detection output from the FM IF IC (IC301) passes
through a noise amplifier (Q301) to detect noise. A voltage is
applied to the CPU (IC101). The CPU controls squelch ac-
cording to the voltage (SQIN) level. The signal from the RSSI
pin of IC301 is used for S-meter. The electric field strength of
the receive signal can be known before the SQIN voltage is
input to the CPU, and the scan stop speed is improved.
Wide/Narrow switching circuit
AF signal system
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC401 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output signal
is buffer amplified by Q410, then divided in IC401 by a dual-
module programmable counter. The divided signal is com-
pared in phase with the 5 or 6.25kHz reference signal in the
phase comparator in IC401. The output signal from the
phase comparator is filtered through a low-pass filter and
passed to the VCO to control the oscillator frequency. (See
The operating frequency is generated by Q406 in trans-
mit mode and Q405 in receive mode. The oscillator fre-
quency is controlled by applying the VCO control voltage,
obtained from the phase comparator, to the varactor diodes
(D405 and D406 in transmit mode and D403 and D404 in
receive mode). The TX/RX pin is set high in receive mode
causing Q408 and Q407 to turn Q406 off, and turn Q405 on.
The TX/RX pin is set low in transmit mode. The outputs
from Q405 and Q406 are amplified by Q410 and sent to the
RF amplifiers. (See Fig. 6.)
IC401 : PLL IC
During reception, the 8RC signal goes high, the 8TC signal
goes low, and Q34 turns on. Q33 turns on and a voltage is
applied to 8R. During transmission, the 8RC signal goes low,
the 8TC signal goes high and Q36 turns on. Q35 turns on and
a voltage is applied to 8T.
The CPU monitors the PLL (IC401) LD signal directly.
When the PLL is unlocked during transmission, the PLL LD
signal goes low. The CPU detects this signal and makes the
8TC signal low. When the 8TC signal goes low, no voltage is
applied to 8T, and no signal is transmitted. (See Fig. 7.)
: LD "H"
The transmitter circuit produces and amplifies the desired
frequency directly. It FM-modulates the carrier signal by
means of a varicap diode.
Power Amplifier Circuit
The transmit output signal from the VCO passes through
the transmission/reception selection diode (D409) and ampli-
fied by Q500, Q501, Q502 and Q503. The amplified signal
goes to the final amplifier (Q504) through a low-pass filter.
The low-pass filter removes unwanted high-frequency har-
monic components, and the resulting signal is transmitted
through the antenna terminal. (See Fig. 8.)
The automatic transmission power control (APC) circuit
detects part of a final amplifier (Q504) output with a diode
(D606, D607) and applies a voltage to IC501. IC501 com-
pares the APC control voltage (PC) generated by the D/A con-
verter (IC161) and DC amplifier (IC203) with the detection
output voltage. IC501 generates the voltage to control Q502,
Q503 and Q504 and stabilizes transmission output.
The APC circuit is configured to protect over current of
Q502, Q503 and Q504 due to fluctuations of the load at the
antenna end and to stabilize transmission output at voltage
and temperature variations. (See Fig. 9.)
The CPU carries out the following tasks (See Fig. 10.):
1) Controls the WIDE, NARROW, TX/RX outputs.
2) Adjusts the AF signal level of the AF filter (IC251) and
turns the filter select compounder on or off.
3) Controls the display unit.
4) Controls the PLL (IC401).
5) Controls the D/A converter (IC161) and adjusts the vol-
ume, modulation and transmission power.
The transceiver has an 64k-bit EEPROM (IC66). The
EEPROM contains adjustment data. The CPU (IC101) con-
trols the EEPROM through three serial data lines. (See Fig.
The CPU (IC101) controls the display LCD and LEDs.
When power is on, the LCD driver will use the BL line to con-
trol the LCD illumination and key backlight LEDs.
The brightness function is controlled by the switch Q12.
The LCD driver (IC3) and CPU (IC101) communicate through
the CE, CL, DI, DO lines. (See Fig. 12.)
Key Matrix Circuit
The TM-471 front panel has function keys. Each of them
is connected to a cross point of a matrix of the KI1 to KI3 and
KS1 to KS2 ports of the LCD driver.
The LCD driver monitors the status of the KI1 to KI3 and
KS1 to KS2 ports. If the state of one of the ports changes,
the LCD driver assumes that the key at the matrix point corre-
sponding to that port has been pressed.
The DCS and CTCSS signals are output from QT/DQT of
the CPU (IC101) and summed with the external pin DI line by
the summing amplifier (IC203) and the resulting signal goes
to the D/A converter (IC161). The DTMF signal is output from
DTMF pin of the CPU and summed with a MIC signal by the
summing amplifier (IC203), and the resulting signal goes to
the D/A converter (IC161).
The D/A converter (IC161) adjusts the MOD level and the
balance between the MOD and CTCSS/DCS levels. Part of a
CTCSS/DCS signal is summed with MOD and the resulting
signal goes to the VCOMOD pin of the VCO. This signal is
applied to a varicap diode in the VCO for direct FM modula-
Key matrix circuit